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LF3312 12-mbit frame buffer / fifo preliminary datasheet logic devices incorporated 1 august 8, 2006 lds.3312 o video imaging product near-full/empty flags with programmable thresholds flexible pointer manipulation ? write and read pointers may be indepen- dently jumped to arbitrary address locations ? write or read pointers can be manipulated in real-time based on external 24bit address LF3312s may be cascaded for depth and width, supporting hdtv, multiframe sdtv, and other high resolution formats ? seamless address space is maintained with up to 16 cascaded devices built-in itu-r bt.656 trs detection and synchronization set & clear read/write pointer control pins choice of control interfaces: ? two-wire serial microprocessor interface ? parallel microprocessor interface input enable control (write mask) for freeze- frame applications output enable control (data skipping) jtag boundary scan - ieee 1149.1 172 ball lbga package 1.8v internal core power supply 3.3v i/o supply dtv/hdtv video stream buffer frame synchronization cctv security camera systems time base correction (tbc) freeze-frame buffer regional read/write for picture-in-picture (pip) field-based or frame-based comb filtering video capture & editing systems deep data buffering video special effects (rotation, zoom) test pattern generation motion detection or frame-to-frame correlation 12,441,600-bit frame memory 74.25mhz max data rate may be organized into the following confgurations: ? 1,555,200 x 8-bit (single channel) ? 1,244,160 x 10-bit (single channel) ? 1,036,800 x 12-bit (single channel) ? 777,600 x 16-bit (width expansion - dual channel) ? 622,080 x 20-bit (width expansion - dual channel) ? 518,400 x 24-bit (width expansion - dual channel) ? 777,600 x 8-bit (each of two parallel channels) ? 622,080 x 10-bit (each of two parallel channels) ? 518,400 x 12-bit (each of two parallel channels) operating modes: ? random access with external address port (single-channel) ? fifo with asynchronous i/o (single-channel) ? fifo with asynchronous i/o (dual-channel) ? synchronous shift register (single-channel) ? synchronous shift register (dual-channel) ? fifo + shift register; channel b synchronized to channel a ? shift register + fifo; one channel synchronized to the other features applications note : this preliminary datasheet references LF3312bgc engineering samples with an es marking under the part designation. devices incorporated
LF3312 12-mbit frame buffer / fifo preliminary datasheet logic devices incorporated august 8, 2006 lds.3312 o video imaging product 2 the LF3312 is a 12,441,600-bit memory device which can be confgured by the user into either a two- data-port single-channel or a four-data-port dual-channel architecture. the input data ports may be clocked simultaneously or asynchronously with one another and with the output ports. using the four 12-bit data ports provided, the user can operate the chip as one or two 8, 10, or 12-bit channels or as a single 16, 20, or 24-bit channel, without wasting any memory resources. since reads are non-destructive, a given data value, once written into the memory core, may be read as many times as desired. a user requiring more storage can cascade up to sixteen LF3312s into a larger array. a great deal of memory addressing fexibility is offered with the LF3312. in addition to simple clearing of the write and read pointers, either pointer may be set/jumped to any location within the entire address space. real-time random-access writing or reading is also supported through an external address port. the device is controlled by sixteen instruction words of eight bits each, which may be programmed or verifed via a standard i 2 c 2-wire serial or parallel microprocessor interface. the 3-bit opmode control selects one of the chips operating modes, each of which has versatile submode options: - one-channel fifo with asynchronous i/o - two-channel fifo; both channels sychronized to external signals - one-channel synchronous shift register (single clock; user-set latency) - two-channel synchronous shift register (single clock; user-set latencies) - one-channel framestore with random access - two-channel fifo; channel a synchronized to channel b - two-channel fifo; channel b synchronized to channel a LF3312 overview LF3312 functional block diagram devices incorporated memory 12mbi t jta g paralle l interface write pointer read pointer random access addressing flag s inpu t data port s output data port s a/b wen a/b re n a/b se t rset a/b ien a /b mark tdi tdo trst tms tclk (x8,x10, x12) two-wire serial interfac e inpu t control outpu t control a /b wclk a/b cl r rclk rclr a/b pe a/b pf a/b collide sda sc l (x8,x10, x12) ce we re addr data ai n bi n aout bout 8 6 load program . . . .
LF3312 12-mbit frame buffer / fifo preliminary datasheet logic devices incorporated august 8, 2006 lds.3312 o video imaging product 3 figure 1. dual channel fifo mode functional block diagram devices incorporated memor y cell arra y a ai n 11- 0 12 bi n 11- 0 12 aout 11- 0 12 bout 11- 0 * 12 bo e ao e 518,400 x 12-bi t 622,080 x 10-bi t 777,600 x 8-bit memor y cell arra y b 518,400 x 12-bi t 622,080 x 10-bi t 777,600 x 8-bit ape apf flag generator a writ e control a aset aclr awen awcl k read control a rset rcl r rcl k aren bpe bpf flag generator b read control b rcl k amar k acollide, bcollide rset rcl r awcl k amar k bwcl k bmar k bren aien writ e control b bset bclr bwen bwcl k bmar k bien master control i c 2 sc l sd a progra m chip_addr 6- 0 7 pdata 8 p a d d r 6 cs b re b w e b
LF3312 12-mbit frame buffer / fifo preliminary datasheet logic devices incorporated 4 august 8, 2006 lds.3312 o video imaging product figure 2. single channel fifo mode functional block diagram figure 3. random access mode functional block diagram memor y cell arra y d[11:0] 12 q[11:0] 12 oe 2,073,600 x 12-bit 2,488,320 x 10-bit 3,110,400 x 8-bit addres s cont ro l read control rcl k re n rset rcl r 24 write control a wset wclr wen wclk mark wien master control i c 2 sc l sda progra m chip_addr 6- 0 7 pdata 8 pad d r 6 pc e 1 pc e 0 pr e pwe 24 addr [ 23: 0 ] write addres s read addres s raddrsel waddrse l devices incorporated memor y cell arra y d[11:0] 12 q[11:0] 12 pe pf flag generato r oe 2,073,600 x 12-bit 2,488,320 x 10-bit 3,110,400 x 8-bit read control read control a rcl k re n rset rcl r collide mark write control a wset wclr wen wclk wien maste r control i c 2 sc l sda progra m chip_addr 6- 0 7 pdata 8 pad d r 6 pc e 1 pc e 0 pr e pwe write addres s read addres s
LF3312 12-mbit frame buffer / fifo preliminary datasheet logic devices incorporated august 8, 2006 lds.3312 o video imaging product 5 operating modes asynchronous single-channel fifo mode (opmode = 3) in opmode 3, the LF3312 is conf gured as a single channel first-in-first-out 12mbit memory, with independent read and write clocks to allow for asynchronous operation. this mode is ideal for buffering or burst data applications. arbitrary write/read pointer jumping is supported in all fifo modes. in this mode the device can re-time a data stream according to a read sync signal (rset or rclr) and either itu-r656 timing reference signals (trs) embedded within the incoming (video) data or the falling edge of a write sync signal applied to aclr, aset, or amark. as a single channel fifo, the LF3312 must have awclk and bwclk tied together as must be awen with bwen, and aien with bien. the input (write) and output (read) clocks need not be synchronous with one another, although the memory core will eventually fll or empty if they differ in average frequency. after it flls, the LF3312 continues writing and the oldest data gets written over. if the memory core empties (and neither the read nor write pointer have been set or cleared during run-time) the read pointer stops incrementing, and the device re-reads the last written sample until more data is written. in either case, when the read and write addresses reach equality, the acollide fag will go high, to alert the host. the almost-full and almost-empty fags provide advance warning of these conditions whenever user-selected fullness or emptiness thresholds, expressed in approximate eightieths of the memory core size, are exceeded. for example, if the 1/80 and 79/80 thresholds are enabled, fag ape will go high whenever the read pointer lags behind the write pointer by less than 1/80 of the memory space, and fag apf will go high whenever the read pointer leads the write pointer by this amount. (calculations are performed modulo the total address space.) the data input and output are sequential and the timing between write and read sync signals dynamically determines the effective delay (depth) of the fifo. the stop reading when empty fifo-mode behavior can be avoided by making sure load is high and issuing any write or read pointer set or clr command at any time. this effectively gets the device out of this read-pointer-halting mode from that point onwards, but invalidates the fags. random access mode allows free manipulation of the r/w pointers, and never halts the read pointer without being commanded to do so using aren or bren. since random access mode naturally increments the r/w pointers sequentially, like in fifo mode, it may be a better mode to use if pointer manipulation of a single-channel of memory is desired. dual-channel asynchronous fifo mode (opmode = 7; power-on default) opmode 7 operates identically to the single channel fifo (opmode 3), with two independent chanels. in dual-channel asynchronous fifo mode, the device can accept two asynchronous data streams and automatically adjust the latency of each to bring it into alignment with an output sync signal applied to rset or rclr. again, the user may reference input synchronization either to aclr, aset, bclr, and bset, to amark and bmark, or to embedded trs. the data read/output clock need not be synchronous with either of the two input clocks, which likewise need not be synchronous with one another. if memory core a or b empties or flls completely, acollide and/or bcollide respectively, will be set accordingly if the write and read pointers collide. the data word that bmark marks (by going low during that xwclk cycle) in the input data stream will be the frst synchronized aout/bout data word. if n full frames of channel a data have been loaded into ain before the frst channel b data frame is loaded into bin, the second frame of b channel data will be synchronized to the (n+1)th channel a frame. (there will be n frames difference between channel a and b). devices incorporated
LF3312 12-mbit frame buffer / fifo preliminary datasheet logic devices incorporated 6 august 8, 2006 lds.3312 o video imaging product single-channel synchronous shift register mode (opmode = 0) in opmode 0, the LF3312 becomes a single channel shift register with programmable total latency up to 2 24 -8 clock cycles. writes and reads occur simultaneously, hence synchronous operation. in opmode 0, the user provides a single clock for both the input and output clocks and specifes a desired input-to-output data path latency, (alat) via the control interface. awclk, bwclk, and rclk must be tied together, as should awen, bwen, aren, and bren. when activated, alat will begin to countdown, and once expired, will allow the inputs to begin to appear on the outputs. in opmode 0, alat countdown can be activated in two ways. the frst occurs when the frst enable is brought low after the load signal has been set high after mpu programming. the second is by bringing load high once mpu programming complete, after the enables have been brought low. dual-channel synchronous shift register mode (opmode = 4) the operation of dual-channel shift register mode is identical to single-channel operation, with the addition of a second independent channel. the latency for each channel is independent and set by the user. the user must also supply a single clock to tie awclk, bwclk, and rclk together, and must load the respective desired constant latency for each channel, (alat, blat), via the microprocessor bus. alat and blat are activated in the same manner as in opmode 0, with the respective inputs being made available on the outputs once alat or blat expire. in this mode, awen and aren must be tied together, as must be bwen and bren. dual-channel master/slave mode (opmode = 5) opmode 5 is one of two master/slave synchronizing modes where two data streams are written into the LF3312 at independent rates and with independent trs timing information. in this mode, both channels are synchronized together based on the sync data supplied to channel a or by the embedded trs data within the a channel. when in opmode 5, channel a operates as a fully synchronous master shift register, to which the data in asynchronous fifo channel b is re-timed. the user drives awclk and rclk from the incoming ain data streams sample clock, and bwclk from the bin data streams clock. the user also specifes whether sync timing will be derived from trs words embedded within the incoming data streams or from signals applied to aclr and aset or to amark and bmark. awen, aren and bren must be tied together to maintain constant reference latency through channel a and to synchronize the outputs. when a mark occurs, the signal mark_active_rset when set high, allows the read pointer to be set to the current value of the write pointer alat rclk cycles later. if the user sets mark_active_rset = 0, the LF3312 will ignore the internal read pointer set. dual-channel slave/master mode (opmode = 6) opmode 6 is the reverse of opmode 5, with the difference being that the two streams are synchronized to the timing information applied to the b channel or embedded within the b channel as trs data. this opmode is identical to the previous, except that channel a is the slave fifo and channel b is the master shift register, and rclk needs to be tied to bwclk, and bwen needs to be tied to bren and aren. similarly to mode 5, when a mark occurs, the signal mark_active_rset when set high, allows the read pointer to be set to the registered value of the write pointer blat number of rclk cycles later. if the user sets mark_active_rset = 0, the LF3312 will ignore the internal read pointer set. operating modes devices incorporated
LF3312 12-mbit frame buffer / fifo preliminary datasheet logic devices incorporated august 8, 2006 lds.3312 o video imaging product 7 random access mode (opmode = 1) random access mode is a single-channel fifo mode, with the capability of either full-time write or read pointer random accessability. this mode also supports write and read pointer jumps to arbitrary locations throughout the address space. unlike asynchronous single-channel fifo mode (opmode=3), random access mode does not disable memory reads when the read pointer catches up to the write pointer. write pointer manipulation can be done through setting (jumping) the write pointer to the 24bit address via the bin and bout ports or to the alatency confguration register. read pointer manipulation can be done through setting (jumping) the write pointer to the 24bit address via the bin and bout ports or to the blatency confguration register. periodic write and read pointer jumping can be accomplished by supplying an address through either the bout/bin address or the a or blatency registers. continuous random access can only be accomplished through the use of the bout/bin ports. when the write/read pointers are not being set to an address, they increment sequentially. in opmode 1, when bset = 1 and bclr = 0 the write pointer is set to the address supplied by the bout/bin ports when aset is brought low. awclk and bwclk must be tied together as must awen and bwen. in other words, on each active write clock cycle (rising edge of awclk for which awen was low two rising edges of awclk previously), the user directs the write pointer to any desired memory location, using what are otherwise the second channel data input and output ports. in this application, bout[11:0] denotes the vertical (row) component, and bin[11:0], the horizontal (column) component, of a cartesian set. setting the control register row_length to the frames line (row) length internally defnes the cartesian coordinates. or, if desired, the concatenation of bout[11:0] in front of bin[11:0] represents a single 24-bit linear address. the user governs the mapping of (bout,bin) to the internal memory space by setting the parameter row_length such that address = bout * row_length + bin. a row_length setting of 0 is interpreted as 4096, such that address = a 24-bit concatenation of {bout,bin} for this particular value. for a standard d1 video application with 1716 samples per line, the user would set row_length to 1716 decimal = 6b4 hex. offset circuitry within the LF3312 permits the user to cascade several chips in parallel and to use them collectively as a single large memory with a seamless address space. data are read out sequentially by rising edges of rclk, under the control of aren (read enable), rset (read pointer force to constant), and rclr (read pointer clear to 0). holding aset low keeps the device continuously in random access write mode. releasing aset to its high state causes the chip to continue to write sequentially from the last-loaded address. in opmode 1, when bclr = 1, bset = 0, mark_sel = 1, the read pointer is set to the address supplied by the bout/bin ports when rset is brought low. awclk and bwclk must be tied together as well as aren and bren. as mentioned above, bout[11:0] represents the upper bits or the vertical (row) address, whereas bin[11:0] represents the lower bits or the horizontal (column) address. releasing rset high causes the read address pointer to increment from its last assigned location to the next sequential address. operating modes devices incorporated
LF3312 12-mbit frame buffer / fifo preliminary datasheet logic devices incorporated 8 august 8, 2006 lds.3312 o video imaging product cascading devices for depth expansion multiple devices can be cascaded to deepen the address space. the usable 24bit address space is simply extended for every additional device that is cascaded. internally, the LF3312 has a 24bit address space. when cascading LF3312s, each devices write and read pointers behave identically. the LF3312 was designed to be cascaded in parallel. that is, the inputs of each device are tied together. the input data word (the data word placed on the ain input port) is to be common for all devices. similarly, the outputs of all devices are tied together. only one device drives the shared output bus at one time, controlled automatically through internal bus enables. each device in a cascade of n devices is responsible for 1/n of the address space. that is, each device writes and/or reads based on the common w/r pointer locations and where that particular device sits in the cascade. confguration register c[3:0] (base_addr) is used to defne each devices place in the cascade. when cascading LF3312s, only singe-channel modes are supported (opmodes 0 to 3). all write enables awen/bwen and aien/bien must be tied together, as must read enables aren/bren (see the device connection diagram below). the confguration registers of each device must be programmed identically, depending on mode/function, except for register c. register c defnes which region of the 24bit address space the particular device is responsible for. within register c, there is a 4bit base_addr and 4bit cascade word. base_addr determines the region of address space each device controls, and cascade defnes how many devices are in cascade. register c effectively is programmed as chip n of n. figure 4. 24mbit fifo depth expansion: two cascaded devices bwcl k aren aset rset bset awcl k acl r rcl k rcl r bi n aout bout ai n awen bwen aien bcl r bien bren LF3312_1 bwcl k aren aset rset bset awcl k acl r rcl k rcl r bi n aout bout ai n awen bwen aien bcl r bien bren LF3312_2 . . . . . . . . . . . . . . . aset bset wclk acl r we n ie n bcl r addr 11- 0 addr 23-12 aout 11- 0 ai n 11- 0 ren rset rcl k rcl r 12 12 12 12 . . . . devices incorporated
serial mpu interface figure 7 - i 2 c start and stop signals programming the LF3312 LF3312 12-mbit frame buffer / fifo preliminary datasheet logic devices incorporated 9 august 8, 2006 lds.3312 o video imaging product device confguration the LF3312 has two mpu interfaces. the frst is a standard two wire serial interface following the i 2 c protocol. the second is a parallel interface allowing the user to write a byte of data at a time to the confguration registers. when the user wishes to use the serial interface, the program pin must be set low, while a high selects the parallel interface. to provide users with more fexibility, the control registers have been combined with a working latch . ultimately, the register-latch combination allows users to update the confguration registers during chip operation, and then to transfer the register contents to all working latches simultaneously using the load signal. when high, the load signal allows the LF3312 to be pre-programmed during operation, and once brought low after programming updates the working latches allowing the new changes to take effect. load can also be maintained low to allow changes to the confguration registers to be immediately refected in the working latches. when the program pin is low, the serial interface is active. up to 16 LF3312 devices can be connected to and programmed by the serial interface. the two wire interface is composed of an scl clock pin and a bi-directional sda data pin. when inactive, sda and scl are forced high by external pull up resistors. data transmission is achieved over the sda pin and must remain constant during the logical high portion of the scl clock pulse. the level of sda, while scl is high, is interpreted as the appropriate bit value as will be shown later. changing the data on sda must only occur when scl is low, because any changes to sda while scl is high is interpreted as a start or stop request, which are shown in figure 7 with an example data transfer in figure 8. the frst operation to begin programming the LF3312 through the serial interface, is to send a start signal. when the interface is inactive, a high to low transition must be sent on sda while scl is high, notifying all connected devices (slaves) to expect a data transmission. when transferring data, the msb of the eight bit sequence is the frst bit to be transmitted to or from the master or slave. the frst byte of data to be transmitted on sda must consist of the 7-bit base address of the slave, along with an 8th read/write bit as the lsb, which describes the direction of the data transmission. the slave whose 7-bit chip_addr6-0, matches the 7-bit base address sent on sda, will send an acknowledgement back to the master by bringing sda low on the 9th scl pulse. during a write operation, if the slave does not send an acknowledgment back to the master device, sda is left high which forces the master to generate a stop signal. in contrast, during a read operation, if there is no acknowledgement back from the master device, the LF3312 interprets this as if it were the end of the data transmission, and leaves sda high, allowing the master to generate its stop signal. devices incorporated scl sda start signal scl sda stop signal
figure 8 - i 2 c example of transferring 11001101 on sda parallel mpu interface LF3312 12-mbit frame buffer / fifo preliminary datasheet logic devices incorporated august 8, 2006 lds.3312 o video imaging product 10 device confguration there are four operations that can be performed between the master and the slave. they are: write to consecutive registers, write to a single control register, read from consecutive registers and read from a single register. to write to consecutive control registers, a start signal and base address must be sent with the r/w bit as described above. after the acknowledgment back from the appropriate slave, the 8-bit address of the target control register must be written to the slave with the r/w bit low. the slave then acknowledges by setting sda low. the data byte to be written into the register can now be transferred on sda. the slave then acknowledges by pulling sda low on the next positive going pulse of scl. the frst control register address loaded into the LF3312 is considered as the beginning address for consecutive writes, and automatically increments to the next higher address space. therefore after the acknowledgement, the data byte to confgure register (frst address + 1) can now be transferred from master to slave. at any point a stop signal can be given to end the data transfer. to write to a single control register, the same technique can be applied adding a stop signal after the f rst data write. to read from consecutive control registers, the master must again give the start signal followed by a base address with the r/w bit = 0, as if the master wants to write to the slave. the appropriate slave then acknowledges. the master will then transfer the target register address to the slave and wait for an acknowledge. the master will then give a repeated start signal to the slave, along with the base address and r/w bit this time high signifying a read and wait for an acknowledge. the user must write to the LF3312 to select the appropriate initial target register. otherwise the starting position of the read is uncertain. once the LF3312 acknowledges, the next byte of data on sda is the contents of the addressed register sent from the device. if the master acknowledges, the LF3312 will send the next higher registers contents on the following byte of data. to read from only one register is the same procedure as for consecutive reading with a stop signal following the transfer of the registers contents. the parallel mpu interface can be used to write instructions to the control registers or to read them back for verifcation. when the program pin is high, the parallel interface is selected. an external processor can write into an internal register by setting paddr to the desired register address, selecting the chip using the csb pin, setting pdata to the desired value and then pulsing web low. the data will be written into the selected register when both web and csb are low, and will be held when either signal goes high. to read from a control register the processor must set paddr to the desired address, select the chip with the csb pin, and then set reb low. the chip will then drive pdata with the contents of the selected register. after the processor has read the value from pdata, reb and csb should be set high. the pdata pins are turned off (high impedance) whenever csb or reb are high or when web is low. the chip will only drive these pins when both csb and reb are low and web is high. one can also ground the reb pin and use the web pin as a read/write direction control and use the csb pin as a control i/o strobe. scl 1 2 3 4 5 6 7 sda 8 devices incorporated
device confguration figure 5 - normal reading and writing from a control register parallel interface contd figure 6 - reading and writing from a control register with reb held low LF3312 12-mbit frame buffer / fifo preliminary datasheet logic devices incorporated 11 august 8, 2006 lds.3312 o video imaging product devices incorporated pcex pcex pdata[7:0] paddr[5:0] t cs u t cs u t cz t cdl y pwe pre pdata[7:0] paddr[5:0] t cs u t cs u t chd t cspw pwe pre write cycle - normal mode read cycle - normal mode t cs u t cs u t cspw t cs u pcex pcex pdata[7:0] paddr[5:0] t cs u t cz t cdl y pwe pdata[7:0] paddr[5:0] t cs u t chd pwe write cycle - pre held lo w read cycle - pre held lo w t cspw t cspw t cs u
LF3312 12-mbit frame buffer / fifo preliminary datasheet logic devices incorporated august 8, 2006 lds.3312 o video imaging product 12 power clocks inputs detailed signal defnitions vcc int - internal core power supply +1.8v power supply. all pins must be connected. vcc o - output driver power supply +3.3v power supply. all pins must be connected. awclk - write clock a data present on ain11-0 is written into the LF3312 on the rising edge of awclk when awen was low for the previous rising edge of awclk. bwclk - write clock b in two-channel modes(opmodes 4-7), data present on bin11-0 is written into the LF3312 on the rising edge of bwclk when bwen is low. in one-channel modes(opmodes 0-3), bwclk must be tied to awclk. rclk - read clock in single channel modes, data is read from the LF3312 and presented on the output port (aout11-0) after a rising edge of rclk while aren and aoe are low. in two-channel mode, data is also read from the LF3312 and presented on the output port (bout11-0) after a rising edge of rclk while bren and boe are low. ain11-0 - data input a ain11-0 is the 12-bit registered data input port. bit 11 is the msb in all modes. ain1-0 are ignored in 10-bit mode and ain3-0 are ignored in 8-bit mode. any such unused inputs should either be tied to ground or driven to proper logic levels by external logic. bin11-0 - data input b in dual-channel modes (opmodes 4-7), bin11-0 is the 12-bit registered data input port in all dual channel fifo modes. bit 11 is the msb in all modes. bin1-0 are ignored in 10-bit mode and bin3-0 are ignored in 8-bit mode. unused inputs should be tied off to ground or driven to proper logic levels by external logic. in single-channel modes (opmode 0-3), bin11-0 can act as a 24bit external address port (addr). chip_addr6-0 - chip address (ca6-0) chip_addr6-0 determines the LF3312s address on the two-wire microprocessor bus. each LF3312 chips 7-bit two-wire serial microprocessor interface address is equal to its chip_addr6-0. scl - serial clock input scl is a standard two-wire serial microprocessor interface clock pin. with this chip, it functions as a dedicated input, since this part cannot be the master on an two-wire serial microprocessor interface. addr23-0 - external random access read/write address port (opmode 0-3) addr23-0 is a virtual 24-bit memory address port, available in single channel modes. addr23-0 is a concatenation of the bin and bout data ports. bin11-0 specifes addr11-0 (x/column- coordinate) and bout11-0 specifes addr23-12 (y/row-coordinate). the 24bit address is a purely linear address when the instruction register row_length is equal to 0(default). when row_length is a non-zero value, the memory is set to have a row (line) length of row_length. paddr5-0 - parallel microprocessor interface address port paddr5-0 is the 6-bit address port for the parallel microprocessor interface. when inactive, it transitions to a high impedance state. devices incorporated
LF3312 12-mbit frame buffer / fifo preliminary datasheet logic devices incorporated 13 august 8, 2006 lds.3312 o video imaging product pdata7-0 - parallel microprocessor interface data port pdata7-0 is the 8-bit data port for the parallel microprocessor interface. when inactive becomes high impedance. sda - serial data i/o sda is the standard bidirectional data pin of a two-wire serial microprocessor interface. external pullup is required on sda. bout11-0 - data output b in two-channel modes(opmodes 4-7), bout11-0 is the 12-bit registered data output port. bout[11] is always the msb. in 10-bit mode, bits 1 and 0 are tristated. in 8-bit mode, bits 3-0 are tristated. all active bits are updated on each rising edge of rclk when bren is low. in opmode 0-3 , bout11-0 can act as the upper word of the 24bit external address addr if row_length is equal to 0, or y-coordinate address if row_length is some value other than zero. bout11-0 represents a portion of the read address port when executing an rset, if and only if aren=0, marksel=1, bclr=1. bout11-0 represents a portion of the write address portwhen executing an aset, if and only if awen=0, aclr=1, bset=1. for more details on rset and aset, please refer to their signal defnitions. aclr - channel a write pointer clear when aclr is brought low, the next rising edge of awclk will bring the current value on ain[11:0] into memory channel a, address 0. whenever aclr is high, the destination for ain[11:0] will be controlled by aset. the user may program aclr such that either its falling edge or its low state is active. if its low state is active, holding this pin low will hold the write address in its zero position continuously. this control takes effect only when awen is low. bclr - channel b write pointer clear / channel a write random select in dual-channel modes (opmode = 4-7), this pin clears the channel b write pointer, in the same manner that aclr clears the channel a write pointer, and the user may program it to be falling edge or low state active. in single-channel modes (opmode = 0-3), this pin and control marksel govern the action of rset. in opmodes 4-7, this control takes effect only when bwen is low. aset - channel a write pointer set this control is active only when aclr is high. bringing aset low will cause the next rising edge of awclk to bring the current value on ain[11:0] into memory a, at the address specifed by alat, or if opmode = 0-3 and bset = 1, at the address whose cartesian coordinates are present on bout and bin. whenever aset and aclr are high, the next rising edge of awclk will bring the current ain[11:0] data value into the next-higher address in sequence. aset may be programmed to be either edge-triggered, in which case it affects the write pointer for only one clock cycle following a falling edge, after which incrementing resumes, or level-triggered, in which case it affects the write pointer until it is brought high. for continuous random access write operation, holding aset low and programming it to be level-triggered will provide the needed continuous write pointer override. this control takes effect only when awen is low. bset - channel b write pointer set in two-channel modes (opmode = 4-7), this pins impact on the b write pointer is analogous to that of aset on the a write pointer, and the user may program the pins action to be either edge- or level- triggering. in one-channel modes, bset determines whether aset forces the write address pointer to alat (bset = 0) or to bout,bin (bset = 1). in opmodes 4-7, this control takes effect only when bwen is low. input/output controls detailed signal defnition devices incorporated
LF3312 12-mbit frame buffer / fifo preliminary datasheet logic devices incorporated august 8, 2006 lds.3312 o video imaging product 14 amark - channel a write address pointer mark in single-channel mode, bringing this bit low will cause an internal register to store a copy the current value of the write address pointer, for subsequent use in synchronizing the corresponding read address pointer to the same location. unlike aclr and aset, this control does not affect the write pointer value itself. the system must use amark instead of aclr if the entire memory core can be flled between sequential falling edges of the sync reference signal. in contrast, the system must use aclr or aset to establish a defnite relationship between the internal address and the data stream, as in random access read mode. bmark - channel b write address pointer mark (active only in dual channel modes, opmode = 4-7) bringing this bit low will cause an internal register to store a copy the current value of the channel b write address pointer, for use in synchronizing the corresponding read address pointer to the same location. this signal does not affect the value of the memory b write address pointer itself. rset - read address pointer set in dual-channel modes (opmode = 4-7), if aren is low, bringing rset low will force read address pointer a to alat (if mark_sel is high) or to the value most recently captured from using amark (if mark_sel is low). if bren is low, bringing rset low will force read address pointer b to blat (if mark_sel is high) or to the value most recently captured by bmark (if marksel is low). in single-channel modes (opmode = 0-3), if aren is low, bringing rset low will force the read address to the most recently marked value (mark_sel low), to blat (marksel high and bclr low), or to bout,bin (mark_sel is high and bclr is high). this pin may be programmed to be either falling edge or level low active. rclr - read address pointer clear bringing rclr low causes the next rising edge of rclk to force the read address pointer (opmode 0-3) or pointers (opmode 4-7) to zero. this pin may be programmed to be active on its falling edge or in its low state. in single-channel mode, it can reset the read pointer only when aren is low. in dual-channel mode, it can reset read pointer a only if aren is low, and read pointer b only if bren is low. awen - write enable a if awen is low, data on ain11-0 is written to the device on the rising edge of awclk. when awen is high, the device ignores data on ain and holds the write pointer. the user must anticipate the use of awen by one cycle. therefore when desiring not to write a sample, awen must be brought high the cycle before. bwen - write enable b if bwen is low, data on bin11-0 is written to the device on the rising edge of bwclk. when bwen is high, the device ignores data on bin and holds the write pointer. the user must anticipate the use of bwen by one cycle. therefore when desiring not to write a sample, bwen must be brought high the cycle before. in single channel modes (opmodes 0-3), bwen must be tied to awen. aien - memory write enable a (write masking) aien is used to enable/disable writing into the memory core. a low on aien enables writing, while a high on aien disables writing. the internal a write address pointer is incremented by awen regardless of the aien level. unless writing into memory is to be disabled, tie aien low. bien - memory write enable b (write masking) bien is used to enable/disable writing into the memory core. a low on bien enables writing, while a high on bien disables writing. the internal b write address pointer is incremented by bwen regardless of the bien level. unless writing into memory is to be disabled, tie bien low detailed signal defnitions devices incorporated
LF3312 12-mbit frame buffer / fifo preliminary datasheet logic devices incorporated 15 august 8, 2006 lds.3312 o video imaging product aren - read enable a if aren is low and the output port is enabled, data from channel a is read and presented on aout11-0 after td has elapsed from the rising edge of rclk. if aren goes high, the last value loaded into channel a output register will remain unchanged and the read pointer will be held. the user must anticipate the use of aren by one cycle. therefore when desiring not to read a sample, aren must be brought high the cycle before. bren - read enable b if bren is low and the output port is enabled, data from channel b is read and presented on bout11-0 after td has elapsed from the rising edge of rclk. if bren goes high, the last value loaded into channel b output register will remain unchanged and the read pointer will be held. the user must anticipate the use of bren by one cycle. therefore when desiring not to read a sample, bren must be brought high the cycle before. program - serial/parallel interface selector when the user wishes to use the serial microprocessor to confgure the LF3312, the program pin must be set low, whereas if he or she wishes to use the parallel interface, program must be set high. load C instruction load bringing asynchronous control load low updates the working instruction latches to match the current contents of the instruction preload latches. holding it low causes the working latches to refect all ongoing instruction preloads. holding it high permits the user to preset the instruction preload latches to any desired confguration without disturbing the work in progress. after any write to the confguration registers, load must be brought high for one cycle, and can then be brought and left low if so desired. reset - global reset bringing synchronous control reset low forces all state machines and read and write pointers to 0 and holds them there until it is released high. it also forces the confguration registers to their default states, if and only if load is also low. the user may then modify the control registers as necessary. bringing reset low while holding load high will reset the state machines and pointers, but will not change either the preload or the working latches. aoe - output enable a when aoe is low, aout11-0 is enabled for output. when aoe is high, aout11-0 is placed in a high- impedance state. in 10-bit modes, aout1-0 are unconditionally tristated. in 8-bit modes, aout3-0 are tristated. the fag outputs are not affected by aoe. boe - output enable b in any dual-channel mode, when boe is low, bout11-0 is enabled for output. when boe is high, or in any single-channel mode, bout11-0 is placed in a high-impedance state. in 10-bit modes, bout1-0 are tristated. in 8-bit modes, bout3-0 are tristated. the fag outputs are not affected by boe. csb - chip enable when low, csb enables writing to the LF3312 with the parallel micrprocessor interface. web - parallel microprocessor interface write enable when low, we enables writing to the LF3312s instruction registers with the parallel micrprocessor interface. reb - parallel microprocessor interface read enable when low, re enables reading from the LF3312s instruction registers with the parallel micrprocessor interface. detailed signal defnitions devices incorporated
LF3312 12-mbit frame buffer / fifo preliminary datasheet logic devices incorporated august 8, 2006 lds.3312 o video imaging product 16 aout11-0 - data output a aout11-0 is the 12-bit registered data output port. aout[11] is always the msb. in 10-bit mode, bits 1 and 0 are tristated. in 8-bit mode, bits 3-0 are tristated. all active bits are updated on each rising edge of rclk when aren is low. bout11-0 - data output b in opmodes 4-7, bout11-0 is the 12-bit registered data output port. bout[11] is always the msb. in 10-bit mode, bits 1 and 0 are tristated. in 8-bit mode, bits 3-0 are tristated. all active bits are updated on each rising edge of rclk when bren is low. in opmodes 0-3 refer to the input description of bout11-0. apf / bpf - programmable almost full flag a & b apf / bpf goes high (active) when the write pointer is more than (max_depth - (max_depth x th)) locations ahead of the read pointer. th is a threshold value stored in the register 9 [2:0]. apf is updated on the rising edge of awclk. in dual-channel mode, bpf is updated on the rising edge of bwclk. trs bits from ain or aout can be mapped to apf (register b[3:0]). in dual-channel mode, trs bits from bin or bout can be mapped to bpf (register b[7:4]). ape / bpe - programmable almost empty flag a & b ape / bpe goes high (active) when the write pointer is less than or equal to (max_depth - (max_depth x tl)) locations ahead of the read pointer. tl is a threshold value stored in the register 9 [2:0]. ape is updated on the rising edge of rclk. in dual-channel mode, bpf is updated on the rising edge of rclk. trs bits from ain or aout can be mapped to ape (register b[3:0]). in dual-channel mode, trs bits from bin or bout can be mapped to bpe (register b[7:4]). acollide - memory read/write pointer collision flag a this fag goes high whenever the read and write addresses to the memory core (single-channel modes) or its a channel (dual-channel modes) coincide. by monitoring the partial full/empty fags, the user can ascertain the direction of approach, i.e., read pointer catching up with write (fifo empty) or write pointer catching up with read (fifo full). trs bits from ain or aout can be mapped to acollide (register b[3:0]). bcollide - memory read/write pointer collision flag b in dual-channel modes, this fag goes high whenever the read and write addresses to the channel b memory core coincide. by monitoring the partial full/empty fags, the user can ascertain the direction of approach, i.e., read pointer catching up with write (fifo empty) or write pointer catching up with read (fifo full). trs bits from bin or bout can be mapped to bcollide (register b[7:4]). tdi - jtag input data tdi is the input data pin when using jtag. tdo - jtag output data tdo is the output data pin when using jtag. trstb - jtag reset trstb is used to reset all the registers and state machine fount the the jtag module. data outputs detailed signal defnitions jtag flag outputs devices incorporated
LF3312 12-mbit frame buffer / fifo preliminary datasheet logic devices incorporated august 8, 2006 lds.3312 o video imaging product 17 the various 8-bit control registers may be pre-programmed with either the parallel microprocessor port (program=1), or through the serial microprocessor interface bus(program=0). changes in pre- programming begin to affect the data path when load is brought low. in each instance, the value in parens () is the default state following assertion of reset while load = 0. instruction register 0 (dft = 00000000) 3:0 = row_length[11:8] (0000: 24-bit linear map; see reg 7) instruction register 1 (dft = 00000000) 7:0 = row_length[7:0] (00000000: 24-bit linear map; see reg 6) instruction register 2 (dft = 00000000) 7:0 = alatency[23:16] (00000000: default = 0; see reg 9, a) instruction register 3 (dft = 00000000) 7:0 = alatency[15:8] (00000000: default = 0; see reg 8, a) instruction register 4 (dft = 00000000) 7:0 = alatency[7:0] (00000000: default = 0; see reg 8, 9) instruction register 5 (dft = 00000000) 7:0 = blatency[23:16] (00000000) instruction register 6 (dft = 00000000) 7:0 = blatency[15:8] (00000000) instruction register 7 (dft = 00000000) 7:0 = blatency[7:0] (00000000) confguration register map tms - jtag tap controller input tms controls the state of the tap controller. tck - jtag clock tck is the used supplied clock of jtag. it controls the fow of data and latches input data on the rising edge. devices incorporated
LF3312 12-mbit frame buffer / fifo preliminary datasheet logic devices incorporated 18 august 8, 2006 lds.3312 o video imaging product instruction register 8 (dft = 10_00_0_111) 7:6 = width[1:0] (10: 10 bits) 5:4 = reserved (make equal to 00) 3 = mark_active_reset (make equal to 0) 2:0 = opmode (111: two-channel asynchronous fifo) instruction register 9 (dft = 00_000_000) 7:6 = trs_sync[1:0] (00: ignore embedded trs) 5 = b_fld (0: frame sync - use falling f-bit from trs) 4 = a_fld (0: frame sync - use falling f-bit from trs) 3 = mark_sel (0: use marked address - not user defned address) 2:0 = flag_set (000: trigger empty, full on 1/80, 79/80) instruction register a (dft = 00000000) 7 = bset_catch (0: setting b pointer does not mark its new value) 6 = aset_catch (0: setting a pointer does not mark its new value) 5 = rset_b_sel (0: rset is falling edge triggered) 4 = rclr_b_sel (0: rclr is falling edge triggered) 3 = bset_b_sel (0: bset is falling edge triggered) 2 = bclr_b_sel (0: bclr is falling edge triggered) 1 = aset_b_sel (0: aset is falling edge triggered) 0 = aclr_b_sel (0: aclr is falling edge triggered) instruction register b (dft = 00_00_00_00) 7:4 = bflag_ctl (00: bpe, bpf are part-empty, -full) 3:0 = aflag_ctl (00: ape, apf are part-empty, -full) instruction register c (dft = 0000_0000) 7:4 = base_addr (0000: lowest-address chip in cascade sequence) 3:0 = cascade (0000: single chip - no cascade of multiple chips) confguration register map tms - jtag tap controller input tms controls the state of the tap controller. tck - jtag clock tck is the used supplied clock of jtag. it controls the fow of data and latches input data on the rising edge. devices incorporated
confguration register defnitions LF3312 12-mbit frame buffer / fifo preliminary datasheet logic devices incorporated august 8, 2006 lds.3312 o video imaging product 19 r egister 0[3:0], r egister 1[7:0] = row_length[11:0] - for cartesian-to-linear address map in single-channel modes this control governs the remapping of cartesian coordinates arriving on bin (horizontal/column compo- nent) and bout (vertical/row component) into a linear address, for use by the chips internal address generator. setting row_length to 0 causes the incoming address to be interpreted directly as a linear address (or equivalently, a cartesian address with 4095 pixels per line), with the 12 bits of bout concatenated with the lesser signifcant 12 bits of bin. r egister 2[7:0], r egister 3[7:0], r egister 4[7:0] = alatency[23:0] - shift register latency (channel a) or 24bit jump address in single-channel synchronous shift register mode (opmode = 0), alatency determines the effective shift register depth, i.e., such that the chips input-to-out latency = tbd + (alatency clock cycles). in dual-channel shift register modes, this register sets the channel a delay. for opmode = 0, 4 or 5, a falling edge on pin amark registers the current value of the write pointer and starts a countdown timer, which forces the read pointer to this registered value alatency clock cycles later. the maximum delay that alat can be made equal to is 2 24 -2 clock cycles. in addition to this function, in all single-channel opmodes, bringing aset low forces/jumps the memory write pointer to the address defned by alatency (when bset is low). thus, when alatency is used to establish a time delay, it is interpreted as an ordinary unsigned binary number. in contrast, when it is used to override an address pointer, alatency defnes an address. when row_length is a non-zero value, alatency[11:0] is equal to the 12-bit x-coordinate (horizontal) and alatency[23:12] is considered the y-coordinate (vertical) in a cartesian coordinate system. when row_length is 0, alatency[23:0] is considered to be a linear address in the memory space. by changing the row_length, the x-coordinate can be from 0 to (row_length-1) to make up the cartesian plane. for example, if row_length = 16, the x-coordinate or alatency[11:0] can be from 0 to 15 in the cartesian space. r egister 5[7:0], r egister 6[7:0], r egister 7[7:0] = blatency[23:0] - shift register depth for (channel b) or 24bit jump address in dual-channel synchronous shift register mode (opmode = 4), blatency determines the effective channel b shift register depth, i.e., such that the chips input-to-out latency = tbd + (blatency clock cycles). in single-channel opmodes, bringing rset low forces/jumps the read pointer to the address defned by blatency. in dual-channel modes, blatency impacts channel b exactly as alatency impacts channel a. total channel b data latency = tbd + (blatency clock cycles). devices incorporated
confguration register defnitions LF3312 12-mbit frame buffer / fifo preliminary datasheet logic devices incorporated 20 august 8, 2006 lds.3312 o video imaging product r egister 8[7:6] = width[1:0] - data word size at input/output ports 0x 8 bits [11:4] xout[3:0] tristated 10 10 bits [11:2] (dft) xout[1:0] tristated 11 12 bits [11:0] r egister 8[5:4] = reserved r egister 8[3] = mark_active_rset 0 ignores the internal rset that occurs following the mark 1 obeys the internal rset according to the mark register 8[2:0] = opmode[2:0] - operating mode 000 1 channel synchronous shift register 001 1 channel random access 010 ------- reserved 011 1 channel asynchronous fifo 100 2 channel synchronous shift register 101 2 channel fifo, b slaved to a 110 2 channel fifo, a slaved to b 111 2 channel asynchronous fifo (default) devices incorporated
confguration register defnitions LF3312 12-mbit frame buffer / fifo preliminary datasheet logic devices incorporated august 8, 2006 lds.3312 o video imaging product 21 register 9[7:6] = trs_sync[1:0] - response to embedded trs eav (a) 00 disable trs sync detection (dft) 01 f-bit of embedded trs eav marks current write pointer. 10 f-bit of embedded trs eav sets current write pointer to value set by bout/bin or alat (1-chnl.modes) or alat & blat (2-chnl. modes, respectively). 11 f-bit of embedded trs eav clears current write pointer. - if b_fld = 0 (frame-based sync), action is on each b-channel eav with f = 0 for which the preceding eav had f = 1. - if b_fld = 1 (feld-based sync), action is on each b-chan eav whose f differs from that of the preceding eav. a_fld affects the ta-channel operation in the same fashion. register 9[5] = b_fld frame/feld sync select, chnl b 0 use only falling f-bit in eav; ignore rising (dft) 1 use both rising and falling f-bit in eav register 9 [4] = a_fld frame/feld sync select, chnl a 0 use only falling f-bit in eav; ignore rising (dft) 1 use both rising and falling f-bit in eav register 9[3] mark_sel - this signal is used in combination with pin bclr to determine to effect of bringing rset low on the read pointer(s). when rset goes to 0: 0 force read pointer(s) to marked address(es) (dft) 1 force read pointer(s) as shown in following table: opmode bclr read pointer equals: 0-3 1 bin/bout address 0-3 0 blat address 4-7 x ch. a=alat, ch. b=blat devices incorporated
confguration register defnitions LF3312 12-mbit frame buffer / fifo preliminary datasheet logic devices incorporated 22 august 8, 2006 lds.3312 o video imaging product register 9[2:0] = flag_set[2:0] - sets fractional fullness and empti- ness thresholds for programmable empty/full flags. full fag goes high when the memory is more than th full. empty fag goes high when the memory is less than or equal to tl full. 000 th = 79/81 (dft) tl = 1/81 (dft) 001 th = 78/81 tl = 2/81 010 th = 77/81 tl = 3/81 011 th = 76/81 tl = 4/81 100 th = 75/81 tl = 5/81 101 th = 74/81 tl = 6/81 110 th = 73/81 tl = 7/81 111 th = 72/81 tl = 8/81 register a[7] = bset_catch - (opmodes 4-7 only) 0: setting write pointer b does not mark its new value (dft) 1: setting write pointer b automatically marks its new value register a[6] = aset_catch - (all opmodes) logic same as above for bset_catch register a[5:0] control action. rb[5] rset_b_sel rb[4] rclr_b_sel rb[3] bset_b_sel rb[2] bclr_b_sel rb[1] aset_b_sel rb[0] aclr_b_sel if 0: each falling edge on the corresponding control pin overrides a memory address counter for exactly one clock cycle, after which normal memory address incrementing immediately resumes. (dft) if 1: the corresponding pin continuously overrides the memory address counter as long as it is held low. memory address incrementing resumes when the pin is returned high. devices incorporated
LF3312 12-mbit frame buffer / fifo preliminary datasheet logic devices incorporated august 8, 2006 lds.3312 o video imaging product 23 register b[7:4] = bflag_ctl[3:0] for pins bpe and bpf * (see below for legend) bflag_ctl bpe bpf bcollide 0000 b empty (r) b full (w) b collide (r) 0001 rb=mb (r) ra=ma (r) b collide (r) 0010 b in f (w) b in v (w) bin h (w) 0011 b out f (r) b out v (r) b out h (r) 0100 b in f (w) b in v (w) b collide (r) 0101 b out f (r) b out v (r) b collide (r) 0110 b in f (w) b in h (w) b collide (r) 0111 b out f (r) b out h (r) b collide (r) 1000 b in v (w) b in h (w) b collide (r) 1001 b out v (r) b out h (r) b collide (r) *each fag is updated on the rising edge of its associated clock: bwclk (w) or rclk (r) ain f, v, h are the trs bits embedded in the incoming a channel trs signals. aout f, v, h are the trs bits embedded in the emerging a channel trs signals. bin f, v, h and bout f, v, h are the analogous b channel values. ra(rb ) is the read address pointer value for channel a(b). ma(mb ) is the marked address pointer value for channel a(b). register b[3:0] aflag_ctl[3:0] for pins ape and apf * aflag_ctl ape apf acollide 0000 a empty (r) a full (w) acollide (r) 0001 rb=mb (r) ra=ma (r) acollide (r) 0010 ain f (w) ain v (w) ain h (w) 0011 aout f (r) aout v (r) aout h (r) 0100 ain f (w) ain v (w) acollide (r) 0101 aout f (r) aout v (r) acollide (r) 0110 ain f (w) ain h (w) acollide (r) 0111 aout f (r) aout h (r) acollide (r) 1000 ain v (w) ain h (w) acollide (r) 1001 aout v (r) aout h (r) acollide (r) *each fag is updated on the rising edge of its associated clock: awclk (w) or rclk (r) confguration register defnitions devices incorporated
LF3312 12-mbit frame buffer / fifo preliminary datasheet logic devices incorporated 24 august 8, 2006 lds.3312 o video imaging product register c[7:4] = base_addr[3:0] - position of chip in cascade series; 0000 = lowest; base_addr[3:0] must not exceed cascade[3:0] register c[3:0] = cascade[3:0] - number of chips in a system with concatenated address spaces. 0000: single chip operation; (dft) sequential r, w addresses, modulo 103,680 0001: two chip cascade; sequential r, w addresses, modulo 207,360 ... ... 1111: sixteen chip cascade; (a) sequential r, w addresses, modulo 1,658,880 (a) note limits regarding the number of possible chips, related to width control: 8bit data: 10 or less LF3312s (width = 0x) 10bit data: 13 or less LF3312s (width = 10) 12bit data: 16 or less LF3312s (width = 11) confguration register defnitions addresses d hex and above are for test purposes only. confguration registers for testing devices incorporated
LF3312 12-mbit frame buffer / fifo preliminary datasheet logic devices incorporated 25 august 8, 2006 lds.3312 o video imaging product storage temperature C65c to +150c v cc int , internal supply voltage with respect to ground C0.5v to + 2.0v vcc o , output drivers supply voltage with respect to ground C0.5v to + 4.0v signal applied to high impedance output C0.5v to + 3.3v output current into low outputs 25 ma latchup current > 400 ma m aximum r atings above which useful life may be impaired (notes 1, 2, 3, 8) o perating c onditions to meet specifed electrical and switching characteristics mode commerica l commerica l temperature range 0c to +70c 0c to +70c supply voltage 1.71v < vcc < 1.89v 3.00v < vcc < 3.60v e lectrical c haracteristics over operating conditions (note 4) symbol parameter test condition min typ max unit v oh v ol v ih v il i ix i ix i oz i cc1 i cc2 i cc3 i cc4 c in c out output high voltage output low voltage input high voltage input low voltage input current input current output leakage current v ccint current, dynamic v ccint current, quiescent v cco current, dynamic v cco current, quiescent input capacitance output capacitance v cc = min., i oh max = -4 ma v cc = min., i ol max = 4 ma (note 3) with internal pull-up - jtag & i2c pins all other pins ground < v out < v cc (note 12) f=55mhz, v ccint =1.9v (note 7) v ccint =1.9v (note 7) f=74mhz, v cco =3.6v (note 6) v cco =3.6v t a = 25c, f = 1 mhz t a = 25c, f = 1 mhz 2.4 2.0 0.4 0.8 +20 ?10 ?10 48 550 12 60 7 7 v v v v a a a ma a ma ma pf pf characteristic vcc int vcc o devices incorporated
LF3312 12-mbit frame buffer / fifo preliminary datasheet logic devices incorporated august 8, 2006 lds.3312 o video imaging product 26 cycle time 1 (awclk,bwclk,rclk) - fifo / sh. reg modes cycle time 2 (awclk,bwclk,rclk) - full-time random access clock pulse width high (awclk,bwclk,rclk) clock pulse width low (awclk,bwclk,rclk) setup time, data inputs (ain,bin) hold time, data inputs (ain,bin) write enable setup time (awen,bwen) write enable hold time (awen,bwen) read enable setup time (aren,bren) read enable hold time (aren,bren) load setup time load hold time r/w set/clr setup time (aclr,bclr,aset,bset,rset,rclr) r/w set/clr hold time (aclr,bclr,aset,bset,rset,rclr) access time write clock to programmable flags (a/bpe,a/bpf,a/bollide) tri-state output disable delay tri-state output enable delay parallel interface control setup time for reads/writes parallel interface control hold time for reads/writes parallel interface control strobe pulse width parallel interface control output delay parallel interface control tristate delay LF3312bgc - symbol parameter t cyc1 t cyc2 t pwh t pwl t ds t dh t wes t weh t res t reh t lds t ldh t rws t rwh t d t f t dis t ena t csu t chd t cspw t cdly t cz min 13.4 18 5 5 5 1 5 1 5 1 5 1 5 1 5 1 20 max 7 7 10 10 8 10 min max switching characteristics commercial operating range (0c to +70c) notes 9, 10 (ns) devices incorporated
write cycle timing - write masking LF3312 12-mbit frame buffer / fifo preliminary datasheet logic devices incorporated 27 august 8, 2006 lds.3312 o video imaging product write cycle timing - write enable read cycle timing t pwh t pw l t cyc1 (n ) (n+1) t ds t dh t we s t we h wclk d[11:0] wien (n+3) (n+4) (n+7) note: wien must be brou g ht high 2 risi n g ed g es of wclk p rior to maski n g in p ut data on d (n+5) data not wr itte n (n+6) data not wr itte n wen = low note: bringing wien high disables data on d from being written into memory, yet it does not disable the write pointer from incr ementing t cyc2 devices incorporated t pwh t pwl t cyc1 t res t reh rclk re n t d q[11:0 ] t f t f oe = low (nC2 ) ( nC1) (n ) (n +1) (n+2 ) (n+3) pe t d collide note: ren should be brou g ht low 2 risi n g ed g es of rclk p rior to ex p ectin g valid data on q t cyc 2 t pwh t pw l (n ) (n+1 ) t ds t dh t we s t we h wclk wen d[11:0] (n+3) (n+4) (n+5) note: wen must be brou g ht low 2 risi n g ed g es of wclk p rior to latchi n g valid data on d ien = low t cyc1 t cyc2
LF3312 12-mbit frame buffer / fifo preliminary datasheet logic devices incorporated august 8, 2006 lds.3312 o video imaging product 28 read reset timing write reset timing random access read pointer jump timing wclk wclr d[11:0] wen = low (n ) (n+1) (0) (1) wset (2) (a) (a+1) t rw s t rw h t rw h 1 t rw s rising edge 1: clears write pointer and latches data on d to be written in address 0 risi n g ed g e 4: sets write pointer to address a ( based on waddr ) and latches data on d to be written in address a * * clr and set both programmed to be falling edge sensitive t ds t dh 2 3 4 5 rcl k rset oe = low t d note: rset programmed to be falling edge sensitive addr 23- 0 q[11:0] (nC2) (n-1) (n) (n +13) t ds t dh 1 13 t d 14 (a) (a+1) note: it takes 14 rising edges of rclk upon setting/jumping the read pointer ( to the 24bit address "a" on addr ) for the contents of location a to be dum p ed onto q a 23 C 0 ren = lo w w addrsel= lo w r addrsel= high opmode[2:0]=001 mark_sel (register 9[3]) =1 rcl k cl r q[11:0] ren = lo w (n ) t rw s 1 note: clr programmed as being falling edge sensitiv e (n+1) (n+2) (n+8) (0) .... 2 8 9 10 (1) t d it takes 9 ren-enabled risi n g ed g es of rclk ( includin g the ed g e that latches a low on cl r ) to p ass the contents of address 0 to the q p ort. devices incorporated
jumping/setting pointers based on confguration register address after remapping process random access write pointer jump timing output enable and disable LF3312 12-mbit frame buffer / fifo preliminary datasheet logic devices incorporated 29 august 8, 2006 lds.3312 o video imaging product devices incorporated wclk we n load t rw h 3 wen is low for 3 rising edges of wclk prior to load transition. it stays low for the minimum required 5 rising edges after th e load transition. set and rset programmed to be level sensitive t rw s t rw h wset rset t rw s t rw h t rw h 1 2 3 4 the configuration registers are programmed while load is low. the load transition triggers the address remap process. wset can be brought low (edge "3") 3 rising edges of wclk after the load transition, jumping the write pointer to the address p rogrammed into the wadr register . rset can be brou g ht low ( ed g e "7" ) 7 risi n g ed g es of rclk after the load transition, j um p in g the read p ointer to the address p ro g rammed into the raddr re g ister. 1 2 3 4 1 2 5 4 7 6 aoe boe aout 11C0 bout 11C0 t dis t ena high imped ance wset note: set programmed to be falling edge sensitive addr 23C0 d [11:0] (n+1) (a) (a+1) (a+2) t ds t dh (a+3) (a+4) note: risi n g ed g e of wclk labeled "1" writes data on d to 24bit address "a" a 23-0 wen= low waddrsel= high opmode[2:0]=001 1 (n) wclk t rw s
LF3312 12-mbit frame buffer / fifo preliminary datasheet logic devices incorporated august 8, 2006 lds.3312 o video imaging product 30 notes 1. maximum ratings indicate stress specifcations only. functional operation of these products at values beyond those indicated in the operating conditions table is not implied. exposure to maximum rating conditions for extended periods may affect reliability. 2. the products described by this specifcation include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. nevertheless, conventional precautions should be observed during storage, handling, and use of these circuits in order to avoid exposure to excessive electrical stress values. 3. this device provides hard clamping of transient undershoot. input levels below ground will be clamped beginning at C0.6 v. the device can withstand operation with inputs or outputs in the range of C0.5 v to +5.5 v. device operation will not be adversely affected, however, input current levels may be in excess of 100 ma. 4. actual test conditions may vary from those designated but operation is guaranteed as speci- fed. 5. i/o ring supply current for a given application can be approximated by: where n = total number of device outputs c = capacitive load per output v = supply voltage f = clock frequency 6. tested in single-channel mode with 14 output pins driving 10pf loads, while toggling at an aver- age of 30% of the 74 mhz clock rate. the 10pf load is estimate of trace and downstream pin capacitance. 7. operating condition assumed to be most demanding reading/writing memory scenario . 8. these parameters are guaranteed but not 100% tested. 9. ac specifcations are tested with input transition times less than 3 ns, output reference levels of 1.5 v (except t dis test), and input levels of nominally 0 to 3.0v. output loading may be a resistive divider which provides for specifed i oh and i ol at an output voltage of v oh min and v ol max respectively. alternatively, a diode bridge with upper and lower current sources of i oh and i ol respectively, and a balancing voltage of 1.5 v may be used. parasitic capacitance is 30 pf minimum, and may be distributed. this device has high-speed outputs capable of large instantaneous current change pulses and fast turn-on/turn-off times. as a result, care must be exercised in the testing of this device. the following measures are recommended: a. a 0.1 f ceramic capacitor should be installed between v cc and ground leads as close to the device as possible. similar capacitors should be installed between device v cc and the tester common, and device ground and tester common. b. ground and v cc supply planes must be brought directly to the device leads . devices incorporated ncv f 2 2
LF3312 12-mbit frame buffer / fifo preliminary datasheet logic devices incorporated 31 august 8, 2006 lds.3312 o video imaging product notes c. input voltages on a test fxture should be adjusted to compensate for inductive ground and v cc noise to maintain required input levels relative to the device ground pin. 10. each parameter is shown as a minimum or maximum value. input requirements are specifed from the point of view of the external system driving the chip. setup time, for example, is specifed as a minimum since the external system must supply at least that much time to meet the worst- case requirements of all parts. responses from the internal circuitry are specifed from the point of view of the device. output delay, for example, is specifed as a maximum since worst-case opera- tion of any device always provides data within that time. 11. for the t ena test, the transition is measured to the 1.5 v crossing point with datasheet loads. for the t dis test, the transition is measured to the ?200mv level from the measured steady-state output voltage with ?10ma loads. the balancing voltage, v th , is set at 3.0 v for z-to-0 and 0-to-z tests, and set at 0 v for z-to-1 and 1-to-z tests. 12. these parameters are only tested at the high temperature extreme, which is the worst case f igure b. t hreshold l evels f igure a. o utput l oading c ircuit s1 i oh i ol v th c l dut devices incorporated oe 0.2 v t di s t en a 0.2 v 1.5 v 1 .5 v 3.0v vt h 1 z 0 z z 1 z 0 1.5 v 1.5 v 0v vt h v ol * v oh * v ol * v oh * measured v ol with i oh = C10ma and i ol = 10ma measured v oh with i oh = C10ma and i ol = 10ma
LF3312 12-mbit frame buffer / fifo preliminary datasheet logic devices incorporated august 8, 2006 lds.3312 o video imaging product 32 speed _ 0c to 70c--commercial screening package and ordering information 172 ball - low profle ball grid array (lbga) LF3312bgc logic devices incorporated reserves the right to make corrections, modifcations, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. logic devices does not assume any liability arising out of the application or use of any product or circuit described herein. in no event shall any liability exceed the purchase price of logic devices products. logic devices products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with logic devices. furthermore, logic devices does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in signifcant injury to the user. ao e_ b aren_b bren_b pa dd r 5 pa dd r 3 pa dd r 0 pr ogram web chip_id 5 chip_id 2 bien_b bwen_b reset_b gnd ao ut 11 v cco rset_b rclr_b pa dd r 4 pa dd r 1 c sb reb chip_id 4 chip_id 1 aien_b aw en_b vc c int ai n 11 ao ut 10 v cco gnd vc c in t pa dd r 2 lo ad_b vc c in t chip_id 6 chip_id 3 vc c in t vc c in t ai n 8 ai n 9 ai n 10 ao ut 8 ao ut 9 v cco gnd gnd vc c in t g nd vc c in t g nd chip_id 0 g nd vc c in t v cco ai n 7 ao ut 5 v cco ao ut 7 g nd ao ut 6 g nd gnd gnd gnd ai n 4 v cco ai n 5 ao ut 3 ao ut 4 v cco gnd ao ut 2 ai n 6 ai n 3 vc c in t ai n 1 ai n 2 ao ut 0 rclk ao ut 1 g nd gnd ai n 0 v cco aw cl k bout 0 v cco bout 1 g nd gnd vc c in t bi n 0 bwcl k bout 3 bout 2 v cco gnd gnd gnd gnd bi n 1 v cco bi n 2 bout 5 bout 4 bout 6 bout 7 g nd gnd gnd gnd bi n 3 g nd bi n 5 bi n 4 bout 8 bout 9 v cco vcco ac lr_b gnd gnd gnd gnd pd at a 2 bi n 6 bi n 8 v cco bi n 7 bout 11 bout 10 v cco bcollide bmark_b vcco pd at a 7 v cco pd at a 4 v cco tck bi n 11 bi n 9 bi n 10 boe_b bpe ac ollide bset_b vcco vcco sd a pd at a 6 v cco pd at a 0 tms tdi gnd vc c in t ape apf bpf aset_b amark_b bclr_b scl pd at a 5 pd at a 3 pd at a 1 trst_b tdo vcco gn d a b c d e f g h j k l m n p 1.00 re f 1.00 re f 1.00 re f 1.00 re f ball p ad corner signal pi n i/o vcc pi n core vcc pi n gnd pi n 1 2 3 4 5 6 7 8 9 10 11 12 13 14 bo tt om view devices incorporated
d ocument t itle : LF3312 12m bit f rame b uffer / fifo rev. j k l m n o ecn no. issue date 03/29/05 04/07/05 04/08/05 08/18/05 09/14/05 08/08/06 description of change cycle time changed to 13.5ns for fast fifo modes fixed pg 17 program pin reference. (pr=0 serial) (pr=1 parallel) cycle time changed to 13.4ns to better refect hd 74.25mhz rate pg 24 vcc text, pg25 i2c descr, pg22 clarifcations on flag operation general clarifcation of op-mode operation text fixed pg32 pin-out pin j1 (signal bin2), fixed cascaded device drawing document history page LF3312 12-mbit frame buffer / fifo preliminary datasheet logic devices incorporated august 8, 2006 lds.3312 o video imaging product 33 devices incorporated

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